# @Author       : Xu Xiaokang
# @Date         : 2025-08-28 21:08:12
# @LastEditors  : Xu Xiaokang
# @LastEditTime : 2025-08-29 23:49:13

# source "C:/_myJGY/17_Markdown/_myOpenSource/Vivado-Tcl/Non-Project-CPU.tcl"
# Complete Non-Project Mode Script with Default Strategy Only

# 记录开始时间
set total_start_time [clock seconds]
set start_formatted_time [clock format $total_start_time -format "%Y-%m-%d %H:%M:%S"]

# 设置准确的源文件路径
set origin_dir "C:/Users/33553/Desktop/VivadoSpeedTest/2024.2/CPU"
set output_dir [file join $origin_dir output]
# 创建输出目录
file mkdir $output_dir

#~ 设置器件 项目名称 顶层模块名 Block Design名 xdc名
set part_name "xc7k70tfbg676-2"
set prj_name CPU
set top_module "top"

# 设置Vivado最大线程为32
set_param general.maxThreads 32

#+++++++++++++++++++++++++++++ read file +++++++++++++++++++++++++++++
# ###############################################
# 第1步：读取Verilog文件
# ###############################################
set read_verilog_start_time [clock seconds]

set verilog_files [list \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/timescale.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/FifoBuffer.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/async_fifo.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/clock_generator.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/fftTop.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgtTop.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_defines.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_alu.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_cfgr.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_cpu.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_ctrl.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dc_fsm.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dc_ram.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dc_tag.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dc_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dmmu_tlb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dmmu_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_dpram_256x32.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_du.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_except.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_freeze.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_genpc.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_gmultp2_32x32.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_ic_fsm.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_ic_ram.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_ic_tag.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_ic_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_if.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_immu_tlb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_immu_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_iwb_biu.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_lsu.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_mem2reg.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_mult_mac.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_operandmuxes.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_pic.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_pm.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_qmem_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_reg2mem.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_rf.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_rfram_generic.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_sb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_sb_fifo.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_spram_2048x32_bw.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_spram_512x20.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_spram_64x14.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_spram_64x22.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_spram_64x24.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_sprs.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_tt.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_wb_biu.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/or1200/or1200_wbmux.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgt/rocketio_wrapper_tile.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgt/rocketio_wrapper_tile_gt.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgt/rocketio_wrapper_tile_gt_frame_check.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgt/rocketio_wrapper_tile_gt_frame_gen.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/mgt/rocketio_wrapper_tile_gt_usrclk_source.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/rtlRam.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_defines.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_crc16.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_crc5.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_ep_rf.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_idma.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_mem_arb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_pa.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_pd.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_pe.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_pl.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_rf.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_utmi_if.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_utmi_ls.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/usbf/usbf_wb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_defines.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_arb.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_master_if.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_msel.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_pri_dec.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_pri_enc.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_rf.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_slave_if.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/wb_conmax/wb_conmax_top.v" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/top.v" \
]

foreach file $verilog_files {
    if {[file exists $file]} {
        read_verilog $file
        puts "INFO: Read Verilog file: $file"
    } else {
        puts "ERROR: Verilog file not found: $file"
        exit
    }
}

set read_verilog_elapsed_time [expr [clock seconds] - $read_verilog_start_time]
puts "INFO: Time taken to read Verilog files: $read_verilog_elapsed_time seconds"

# ###############################################
# 第2步：读取约束文件
# ###############################################
set read_xdc_start_time [clock seconds]

set xdc_files [list \
    "$origin_dir/$prj_name.srcs/constrs_1/imports/kintex7/top.xdc" \
    "$origin_dir/$prj_name.srcs/constrs_2/imports/kintex7/top_full.xdc" \
]

foreach file $xdc_files {
    if {[file exists $file]} {
        read_xdc $file
        puts "INFO: Read XDC file: $file"
    } else {
        puts "WARNING: XDC file not found: $file"
    }
}

set read_xdc_elapsed_time [expr [clock seconds] - $read_xdc_start_time]
puts "INFO: Time taken to read XDC files: $read_xdc_elapsed_time seconds"

# ###############################################
# 第3步：读取VHDL文件（特别注意编译顺序）
# ###############################################
set read_vhdl_start_time [clock seconds]

# 特别注意：bft_package.vhdl 必须第一个编译，它包含了其他模块所需的包定义
if {[file exists "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/bft_package.vhdl"]} {
    read_vhdl -library bftlib "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/bft_package.vhdl"
    puts "INFO: Compiled bft_package.vhdl to library bftlib"
} else {
    puts "ERROR: bft_package.vhdl not found - this file is required for VHDL compilation"
    exit
}

# 然后编译其他依赖于bft_package的模块，注意顺序
set vhdl_bft_files [list \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/core_transform.vhdl" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/round_1.vhdl" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/round_2.vhdl" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/round_3.vhdl" \
    "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bftLib/round_4.vhdl" \
]

foreach file $vhdl_bft_files {
    if {[file exists $file]} {
        read_vhdl -library bftlib $file
        puts "INFO: Compiled [file tail $file] to library bftlib"
    } else {
        puts "WARNING: File $file does not exist"
    }
}

# 最后编译顶层的bft实体
if {[file exists "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bft.vhdl"]} {
    read_vhdl "$origin_dir/$prj_name.srcs/sources_1/imports/Sources/bft.vhdl"
    puts "INFO: Compiled bft.vhdl"
} else {
    puts "WARNING: bft.vhdl not found"
}

set read_vhdl_elapsed_time [expr [clock seconds] - $read_vhdl_start_time]
puts "INFO: Time taken to read VHDL files: $read_vhdl_elapsed_time seconds"

# 计算读取文件总时间
set read_file_elapsed_time [expr {
    $read_verilog_elapsed_time
    + $read_vhdl_elapsed_time
    + $read_xdc_elapsed_time
}]
#-------------------------- read file --------------------------


#++ ==================== Synth begin ====================
set Synth_start_time [clock seconds]

# 明确设置顶层模块（使用变量）
set_property TOP $top_module [current_fileset]

puts "============================================="
puts "PHASE 2: SYNTHESIS (Default Strategy)"
puts "============================================="

# 1.1 综合 - Synth Design (Default)
synth_design -top $top_module -part $part_name

# 1.1 Utilization - Synth Design (Default Report)
report_utilization -file ${output_dir}/Utilization_Synth_Design.rpt

# 1.2 Synthesis Report (由synth_design自动生成，在日志中查看)
puts "INFO: Synthesis Report generated in Vivado log"

write_checkpoint -force ${output_dir}/post_synth.dcp

set Synth_elapsed_time [expr [clock seconds] - $Synth_start_time]
puts "INFO: Synth completed in $Synth_elapsed_time seconds"
#-- ==================== Synth end ====================


#++ ==================== Impl begin ====================
set Impl_start_time [clock seconds]

puts "============================================"
puts "PHASE 3: IMPLEMENTATION (Default Strategy)"
puts "============================================"

# 2.2 Opt Design (opt_design) (Default)
opt_design

# 2.2 DRC - Opt Design (Default Report)
report_drc -file ${output_dir}/DRC_Opt_Design.rpt

# 2.4 Place Design (place_design) (Default)
place_design

# 2.4 IO - Place Design (Default Report)
report_io -file ${output_dir}/IO_Place_Design.rpt

# 2.4 Utilization - Place Design (Default Report)
report_utilization -file ${output_dir}/Utilization_Place_Design.rpt

# 2.4 Control Sets - Place Design (Default Report)
report_control_sets -verbose -file ${output_dir}/Control_Sets_Place_Design.rpt

# 2.6 Post-Place Phys Opt Design (phys_opt_design) (Default)
phys_opt_design

# 2.7 Route Design (route_design) (Default)
route_design

# 2.7 DRC - Route Design (Default Report)
report_drc -file ${output_dir}/DRC_Route_Design.rpt

# 2.7 Methodology - Route Design (Default Report)
report_methodology -file ${output_dir}/Methodology_Route_Design.rpt

# 2.7 Power - Route Design (Default Report)
report_power -file ${output_dir}/Power_Route_Design.rpt

# 2.7 Route Status - Route Design (Default Report)
report_route_status -file ${output_dir}/Route_Status_Route_Design.rpt

# 2.7 Timing Summary - Route Design (Default Report)
report_timing_summary -max_paths 10 -report_unconstrained -file ${output_dir}/Timing_Summary_Route_Design.rpt

# 2.7 Clock Utilization - Route Design (Default Report)
report_clock_utilization -file ${output_dir}/Clock_Utilization_Route_Design.rpt

# 2.7 Bus Skew - Route Design (Default Report)
report_bus_skew -warn_on_violation -file ${output_dir}/Bus_Skew_Route_Design.rpt

# 2.7 implementation log (由route_design自动生成，在日志中查看)
puts "INFO: Implementation log generated in Vivado log"

write_checkpoint -force ${output_dir}/post_route.dcp

set Impl_elapsed_time [expr [clock seconds] - $Impl_start_time]
puts "INFO: Implementation completed in $Impl_elapsed_time seconds"
#-- ==================== Impl end ====================


#++ ==================== Bitstream begin ====================
# 降低 DRC 检查的严重级别（谨慎使用）
# set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
# set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

set Bitstream_start_time [clock seconds]

puts "=================================================="
puts "PHASE 4: BITSTREAM GENERATION (Default Strategy)"
puts "=================================================="

# 2.9 Write Bitstream (Default) - 使用变量命名bit文件
write_bitstream -force ${output_dir}/${top_module}.bit

# 2.9 implementation log (由write_bitstream自动生成，在日志中查看)
puts "INFO: Bitstream implementation log generated in Vivado log"

set Bitstream_elapsed_time [expr [clock seconds] - $Bitstream_start_time]
puts "INFO: Bitstream completed in $Bitstream_elapsed_time seconds"
#-- ==================== Bitstream end ====================


#+++++++++++++++++++++++++ 最后信息输出 ++++++++++++++++++++++++++
set reprot_info "\n==================================="
append reprot_info "\nCOMPLETED - DEFAULT STRATEGY ONLY"
append reprot_info "\n==================================="
append reprot_info "\nTop Module: $top_module"
append reprot_info "\nGenerated DEFAULT reports only:"
append reprot_info "\n"
append reprot_info "\nSYNTHESIS PHASE:"
append reprot_info "\n- Utilization_Synth_Design.rpt (Default)"
append reprot_info "\n- Synthesis Report (自动生成，查看日志)"
append reprot_info "\n"
append reprot_info "\nIMPLEMENTATION PHASE - Default Report:"
append reprot_info "\n- DRC_Opt_Design.rpt"
append reprot_info "\n- IO_Place_Design.rpt"
append reprot_info "\n- Utilization_Place_Design.rpt"
append reprot_info "\n- Control_Sets_Place_Design.rpt"
append reprot_info "\n- DRC_Route_Design.rpt"
append reprot_info "\n- Methodology_Route_Design.rpt"
append reprot_info "\n- Power_Route_Design.rpt"
append reprot_info "\n- Route_Status_Route_Design.rpt"
append reprot_info "\n- Timing_Summary_Route_Design.rpt"
append reprot_info "\n- Clock_Utilization_Route_Design.rpt"
append reprot_info "\n- Bus_Skew_Route_Design.rpt"
append reprot_info "\n"
append reprot_info "\nNON-DEFAULT REPORTS (注释掉，可按需启用):"
append reprot_info "\n# Timing_Summary_Design_Initialization.rpt"
append reprot_info "\n# Timing_Summary_Opt_Design.rpt"
append reprot_info "\n# Incremental_Reuse_Place_Design.rpt"
append reprot_info "\n# Timing_Summary_Place_Design.rpt"
append reprot_info "\n# Timing_Summary_Post_Place_Phys_Opt_Design.rpt"
append reprot_info "\n# Incremental_Reuse_Route_Design.rpt"
append reprot_info "\n# Timing_Summary_Post_Route_Phys_Opt_Design.rpt"
append reprot_info "\n# Bus_Skew_Post_Route_Phys_Opt_Design.rpt"
append reprot_info "\n"
append reprot_info "\nBITSTREAM PHASE:"
append reprot_info "\n- ${top_module}.bit (生成的bit文件)"
append reprot_info "\n- implementation log (自动生成，查看日志)"
append reprot_info "\n"
append reprot_info "\nTotal: 11个Default Report文件生成"
append reprot_info "\n8个非Default Report已注释，可按需取消注释使用"
append reprot_info "\n================================"
append reprot_info "\n=================== COMPLETE TIME SUMMARY ==================="
append reprot_info "\nCompilation started:             $start_formatted_time"

# 最后一次性输出所有内容
puts $reprot_info

# ==================== 完整时间统计 ====================
set total_elapsed [expr [clock seconds] - $total_start_time]

set output "\n=================== COMPLETE TIME SUMMARY ==================="
append output "\nthis project name: $prj_name"
append output "\nCompilation started:             $start_formatted_time"
append output "\nReading source files:            $read_file_elapsed_time seconds"
append output "\nSynthesis:                       $Synth_elapsed_time seconds"
append output "\nImplementation:                  $Impl_elapsed_time seconds"
append output "\nBitstream generation:            $Bitstream_elapsed_time seconds"
append output "\ntime total:                      [expr {
    $read_file_elapsed_time
    + $Synth_elapsed_time
    + $Impl_elapsed_time
    + $Bitstream_elapsed_time
}] seconds"
append output "\n=========================================================="
append output "\nTOTAL COMPILATION TIME:          $total_elapsed seconds"
append output "\n=========================================================="

puts $output
#--------------------------- 最后信息输出 ---------------------------

# start_gui